(1) Field of the Invention
This invention relates to an improved dynamic random access memory cell having an improved trench capacitor that can provide the required capacitance while occupying less surface space, and to a method of fabricating the improved cell.
(2) Description of the Prior Art
In the last decade, semiconductor memories have been the fastest growing segment of the semiconductor industry, with the large expansion due to the rapid growth of the digital electronics market with increasing applications. Of the various types of semiconductor memories, dynamic random access memories (DRAMS) have been produced in the largest quantities because of their high density, low cost, and high performance. An important contribution is the transistor memory cell, which uses a capacitor for storing different amounts of charge to represent different binary logic states. The simple schematic diagram of such a cell utilizing a trench capacitor is illustrated in FIG. 1 of the drawings. The gate electrode 10 of FET 12 is connected by a suitable metallurgy system to the word line of a supporting device. The source 14 of transistor 12 is connected to a bit line, and the drain is connected to electrode 18 of capacitor 20, which is shown located in a trench in order to conserve surface area. Suitable isolation 22 is provided to electrically isolate the cells on the device from each other.
As each new generation of memories has evolved, the chip density has roughly quadrupled. This density increase has been achieved by new and innovative cell designs. Operating requirements and design constraints have in general required that the cell capacitor should store enough charges to prevent noise problems. Since the storage charge capacity of a capacitor is largely dependent on the area of the capacitor elements, new capacitor designs seek to utilize the vertical dimensions of the device by placing the capacitors on the surface in overlying relationship to the device elements, or to bury them in trenches. There is a pressing need in the semi-conductor memory technology to shrink the area that the cell occupies on the wafer to increase the chip density, and yet achieve basically the some storage capacity.